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EL5226, EL5326
Data Sheet June 7, 2004 FN7118.2
10- and 12-Channel TFT-LCD Reference Voltage Generators
The EL5226 and EL5326 are designed to produce the reference voltages required in TFT-LCD applications. Each output is programmed to the required voltage with 10 bits of resolution. Reference pins determine the high and low voltages of the output range, which are capable of swinging to either supply rail. Programming of each output is performed using the I2C serial interface. A number of the EL5226 and EL5326 can be stacked for applications requiring more than 12 outputs. The reference inputs can be tied to the rails, enabling each part to output the full voltage range, or alternatively, they can be connected to external resistors to split the output range and enable finer resolutions of the outputs. The EL5226 has 10 outputs and the EL5326 has 12 outputs and both are available in a 28-pin TSSOP package. They are specified for operation over the full -40C to +85C temperature range.
Features
* 10- to 12-channel reference outputs * Accuracy of 1% * Supply voltage of 5V to 16.5V * Digital supply 3.3V to 5V * Low supply current of 10mA * Rail-to-rail capability
Applications
* TFT-LCD drive circuits * Reference voltage generators
Ordering Information
PART NUMBER EL5226IR EL5226IR-T7 EL5226IR-T13 EL5326IR EL5326IR-T7 EL5326IR-T13 PACKAGE 28-Pin TSSOP 28-Pin TSSOP 28-Pin TSSOP 28-Pin TSSOP 28-Pin TSSOP 28-Pin TSSOP TAPE & REEL 7" 13" 7" 13" PKG. DWG. # MDP0044 MDP0044 MDP0044 MDP0044 MDP0044 MDP0044
Pinouts
EL5226 (28-PIN TSSOP) TOP VIEW
STD_REG 1 SCL 2 SDA 3 OSC 4 OSC_SELECT 5 VS 6 NC 7 VSD 8 REFH 9 REFL 10 VS 11 GND 12 CAP 13 DEV_ADDRO 14 28 NC 27 OUTA 26 OUTB 25 OUTC 24 GND 23 OUTD 22 OUTE 21 OUTF 20 OUTG 19 GND 18 OUTH 17 OUTI 16 OUTJ 15 NC
EL5326 (28-PIN TSSOP) TOP VIEW
STD_REG 1 SCL 2 SDA 3 OSC 4 OSC_SELECT 5 VS 6 NC 7 VSD 8 REFH 9 REFL 10 VS 11 GND 12 CAP 13 A0 14 28 OUTA 27 OUTB 26 OUTC 25 GND 24 OUTD 23 OUTE 22 OUTF 21 OUTG 20 OUTH 19 OUTI 18 GND 17 OUTJ 16 OUTK 15 OUTL
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003-2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners.
EL5226, EL5326
Absolute Maximum Ratings (TA = 25C)
Supply Voltage between VS and GND. . . . . . . . . . . . . . . . . . . .+18V Supply Voltage between VSD and GND . . . . . . . VS and +7V (max) Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER SUPPLY IS Supply Current
VS = 15V, VSD = 5V, VREFH = 13V, VREFL = 2V, RL = 1.5k and CL = 200pF to 0V, TA = 25C, unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
EL5226 EL5326
9 10 0.9
11 12 3.2
mA mA mA
ISD ANALOG VOL VOH ISC PSRR tD VAC VDROOP RINH REG DIGITAL VIH VIL FCLK
Digital Supply Current
Output Swing Low Output Swing High Short Circuit Current Power Supply Rejection Ratio Program to Out Delay Accuracy Droop Voltage Input Resistance @ VREFH, VREFL Load Regulation
Sinking 5mA (VREFH = 15V, VREFL = 0) Sourcing 5mA (VREFH = 15V, VREFL = 0) RL = 10 VS+ is moved from 14V to 16V 14.85 150 45
50 14.95 240 65 4 20 1 34
150
mV V mA dB ms mV
2
mV/ms k
IOUT = 5mA step
0.5
1.5
mV/mA
Logic 1 Input Voltage Logic 0 Input Voltage Clock Frequency
VSD20% 20%* VSD 400
V V kHz
2
EL5226, EL5326 Pin Descriptions
EL5226 1 2 3 4 5 6, 11 7, 15, 28 8 9 10 12, 19, 24 13 14 16 17 18 20 21 22 23 25 26 27 EL5326 1 2 3 4 5 6, 11 7 8 9 10 12, 18, 25 13 14 17 19 20 21 22 23 24 26 27 28 15 16 PIN NAME STD_REG SCL SDA OSC OSC_SELECT VS NC VSD REFH REFL GND CAP DEV_ADDR0 OUTJ OUTI OUTH OUTG OUTF OUTE OUTD OUTC OUTB OUTA OUTL OUTK Digital Power PIN TYPE Logic Input Logic Input Logic Input Input/Output Logic Input Analog Power PIN FUNTION Selects mode, high = standard, low = register mode I2C clock I2C data Oscillator pin for synchronizing multiple chips Selects internal / external OSC source, high = external, low = internal Power supply for analog circuit not connected Power supply for digital circuit
Analog Reference Input High reference voltage Analog Reference Input Low reference voltage Ground Analog Bypass Pin Logic Input Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Ground Decoupling capacitor for internal reference generator I2C device address input, bit 0 Channel J programmable output Channel I programmable output Channel H programmable output Channel G programmable output Channel F programmable output Channel E programmable output Channel D programmable output Channel C programmable output Channel B programmable output Channel A programmable output Channel L programmable output Channel K programmable output
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EL5226, EL5326 Typical Performance Curves
VS=15V, VSD=5V, VREFH=13V, VREFL=2V 0.3 DIFFERENTIAL NONLINEARITY (LSB) 0.2 0.1 ISD (mA) 0 -0.1 -0.2 -0.3 10 1.2 1.0 0.8 0.6 0.4 0.2 0 VS=VREFH=15V VREFL=0V
210
410
610
810
1010
3
3.2
3.4
3.5
3.8
4 VSD (V)
4.2
4.4
4.5
4.8
5
INPUT CODE
FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE
FIGURE 2. DIGITAL SUPPLY VOLTAGE vs DIGITAL SUPPLY CURRENT
VS=VREFH=15V M=400ns/DIV 5mA 0mA CL=4.7nF RS=20 5V CL=1nF RS=20 CL=180pF
VS=VREFH=15V M=400ns/DIV
0mA 5mA
5mA/DIV
CL=1nF RS=20
200mV/DIV CL=4.7nF RS=20 CL=180pF
FIGURE 3. TRANSIENT LOAD REGULATION (SOURCING)
FIGURE 4. TRANSIENT LOAD REGULATION (SINKING)
M=400s/DIV
M=400s/DIV
SCLK 5V 0V SDA 5V 0V 10V 5V 0V OUTPUT
SCLK
SDA
OUTPUT
FIGURE 5. LARGE SIGNAL RESPONSE (RISING FROM 0V TO 8V)
FIGURE 6. LARGE SIGNAL RESPONSE (FALLING FROM 8V TO 0V)
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EL5226, EL5326 Typical Performance Curves (Continued)
M=400s/DIV M=400s/DIV
SCLK 5V 0V SDA 5V 0V OUTPUT 200mV OUTPUT
SCLK
SDA
0V
FIGURE 7. SMALL SIGNAL RESPONSE (RISING FROM 0V TO 200mV)
FIGURE 8. SMALL SIGNAL RESPONSE (FALLING FROM 200mV TO 0V)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.9 0.8 POWER DISSIPATION (W) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 1.333W
TS S
833mW
TS SO P2 12 8 0 C/ W
1.2 POWER DISSIPATION (W) 1 0.8 0.6 0.4 0.2 0 0
JA =
JA =
O P2 8 75 C /W
25
50
75 85
100
125
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 9. POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 10. POWER DISSIPATION vs AMBIENT TEMPERATURE
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EL5226, EL5326 General Description
The EL5226 and EL5326 provide a versatile method of providing the reference voltages that are used in setting the transfer characteristics of LCD display panels. The V/T (Voltage/Transmission) curve of the LCD panel requires that a correction is applied to make it linear; however, if the panel is to be used in more than one application, the final curve may differ for different applications. By using the EL5226 and EL5326, the V/T curve can be changed to optimize its characteristics according to the required application of the display product. Each of the eight reference voltage outputs can be set with a 10-bit resolution. These outputs can be driven to within 50mV of the power rails of the EL5226 and EL5326. As all of the output buffers are identical, it is also possible to use the EL5226 and EL5326 for applications other than LCDs where multiple voltage references are required that can be set to 10 bit accuracy. the Device Address and write/read bit. This address is a 7bit long device address and only two device addresses (74H and 75H) are allowed for the EL5226 and EL5326. The first 6 bits (A6 to A1, MSBs) of the device address have been factory programmed and are always 111010. Only the least significant bit A0 is allowed to change the logic state, which can be tied to VSD or DGND. A maximum of two EL5226 and EL5326 may be used on the same bus at one time. The EL5226 and EL5326 monitor the bus continuously and waiting for the start condition followed by the device address. When a device recognizes its device address, it will start to accept data. An eighth bit is followed by the device address, which is a data direction bit (W/R). A "0" indicates a Write transmission and a "1" indicates a Read transmission. The EL5226 and EL5326 can be operated as Standard mode and Register mode. See the I2C Timing Diagram 1 for detail formats. STANDARD MODE The part operates at Standard Mode if pin 1 (STD/REG) is held high. The Standard Mode allows the user to program all outputs at one time. Two data bytes are required for 10-bit data for each channel output and there are a total of 20/24 data bytes for 10/12 channels. Data in data byte 1 and 2 is for channel A. Data in data byte 15 and 16 is for channel H. D9 to D0 are the 10-bit data for each channel. The unused bits in the data byte are "don't care" and can be set to either one or zero. See Table 1 for program sample for one channel setting:
TABLE 1. DATA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CONDITION Data value = 0 Data value = 512 Data value = 31 Data value = 1023
Digital Interface
The EL5226 and EL5326 use a simple two-wire I2C digital interface to program the outputs. The bus line SCLK is the clock signal line and bus SDA is the data information signal line. The EL5226 and EL5326 can support the clock rate up to 400kHz. External pull up resistor is required for each bus line. The typical value for these two pull up resistor is about 1k. START AND STOP CONDITION The Start condition is a high to low transition on the SDA line while SCLK is high. The Stop condition is a low to high transition on the SDA line while SCLK is high. The start and stop conditions are always generated by the master. The bus is considered to be busy after the start condition and to be free again a certain time after the stop condition. The two bus lines must be high when the buses are not in use. The I2C Timing Diagram 2 shows the format. DATA VALIDITY The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can only change when the clock signal on the SCLK line is low. BYTE FORMAT AND ACKNOWLEDGE Every byte put on the SDA line must be eight bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit first (MSB). The master puts a resistive high level on the SDA line during the acknowledge clock pulse. The peripheral that acknowledges has to pull down the SDA line during the acknowledge clock pulse. DEVICES ADDRESS AND W/R BIT Data transfers follow the format shown in Timing Diagram 1. After the Start condition, a first byte is sent which contains
When the W/R bit is high, the master can read the data from the EL5226 and EL5326. See Timing Diagram 1 for detail formats. REGISTER MODE The part operates at Register Mode if pin 1 (STD/REG) is held low. The Register Mode allows the user to program each output individually. Followed by the first byte, the second byte sets the register address for the programmed output channel. Bits R0 to R3 set the output channel address. For the unused bits in the R4 to R7 are "don't care". See Table 2 for program sample. The EL5226 and EL5326 also allows the user to read the data at Register Mode. See Timing Diagram 1 for detail formats.
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I2C Timing Diagram 1
STANDARD MODE (STD/REG = HIGH) WRITE MODE
I2C Data I2C Data In Start Device Address W A = don't care Data 1 A Data 2 A Data 3 Data 16 A Stop
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5
D2 D1 D0
I2C CLK In
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
6
7
8
7
STANDARD MODE (STD/REG = HIGH) READ MODE
I2C Data I2C Data In Start Device Address R A Data 1 A Data 2 A Data 3 Data 16 NA Stop A6 A5 A4 A3 A2 A1 A0 I2C Data Out D7 D6 D5 D4 D3 D2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D2 D1 D0
EL5226, EL5326
I2C CLK In
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
6
7
8
REGISTER MODE (STD/REG = LOW) WRITE MODE
I2C Data I2C Data In Start Device Address W A Register Address A Data 1 A Data 2 A Stop
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 R3 R2 R1 R0
D7 D6 D5 D4 D3 D2 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
I2C CLK In
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
REGISTER MODE (STD/REG = LOW) READ MODE
I2C Data I2C Data In I2C Data Out D7 D6 D5 D4 D3 D2 D9 D8 I2C CLK In D7 D6 D5 D4 D3 D2 D1 D0 Start Device Address W A Register Address A Start Device Address R A Data 1 A Data 2 NA Stop
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 R3 R2 R1 R0
A6 A5 A4 A3 A2 A1 A0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
EL5226, EL5326
REGISTER ADDRESS R3 0 0 0 0 R2 0 0 0 1 R1 0 0 1 1 R0 0 1 0 1 D9 0 1 0 1 D8 0 0 0 1 D7 0 0 0 1 D6 0 0 0 1
DATA D5 0 0 0 1 D4 0 0 1 1 D3 0 0 1 1 D2 0 0 1 1 D1 0 0 1 1 D0 0 0 1 1 CONDITION Channel A, Value = 0 Channel B, Value = 512 Channel C, Value = 31 Channel H, Value = 1023
I2C Timing Diagram 2
START CONDITION tR tF STOP CONDITION
DATA
CLOCK tS tH tR tF
tS
tH
falling OSC clock edges. The output refreshed switches open at the rising edges of the OSC clock. The driving load shouldn't be changed at the rising edges of the OSC clock. Otherwise, it will generate a voltage error at the outputs. This clock may be input or output via the clock pin labeled OSC. The internal clock is provided by an internal oscillator running at approximately 21kHz and can be output to the OSC pin. In a 2 chip system, if the driving loads are stable, one chip may be programmed to use the internal oscillator; then the OSC pin will output the clock from the internal oscillator. The second chip may have the OSC pin connected to this clock source. For transient load application, the external clock Mode should be used to ensure all functions are synchronized together. The positive edge of the external clock to the OSC pin should be timed to avoid the transient load effect. The Application Drawing shows the LCD H rate signal used, here the positive clock edge is timed to avoid the transient load of the column driver circuits. After power on, the chip will start with the internal oscillator mode. At this time, the OSC pin will be in a high impedance condition to prevent contention. By setting pin 32 to high, the chip is on external clock mode. Setting pin 32 to low, the chip is on internal clock mode.
FIGURE 11. START, STOP & TIMING DETAILS OF I2C INTERFACE
Analog Section
TRANSFER FUNCTION The transfer function is:
data V OUT ( IDEAL ) = V REFL + ------------ x ( V REFH - V REFL ) 1024
where data is the decimal value of the 10-bit data binary input code. The output voltages from the EL5226 and EL5326 will be derived from the reference voltages present at the VREFL and VREFH pins. The impedance between those two pins is about 32k. Care should be taken that the system design holds these two reference voltages within the limits of the power rails of the EL5226 and EL5326. GND < VREFH VS and GND VREFL VREFH. In some LCD applications that require more than 12 channels, the system can be designed such that one EL5226 or EL5326 will provide the Gamma correction voltages that are more positive than the VCOM potential. The second EL5226 or EL5326 can provide the Gamma correction voltage more negative than the VCOM potential. The Application Drawing shows a system connected in this way. CLOCK OSCILLATOR The EL5226 and EL5326 require an internal clock or external clock to refresh its outputs. The outputs are refreshed at the
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EL5226, EL5326 Block Diagram
REFERENCE HIGH
OUTA
OUTB
OUTJ EIGHT CHANNEL MEMORY VOLTAGE SOURCES OUTK
OUTL
REFERENCE LOW REFERENCE DECOUPLE I2C DATA IN I2C CLOCK IN CONTROL IF
FILTER
STD/REG
A0
OSCILLATOR SELECT
OSCILLATOR INPUT/OUTPUT
CHANNEL OUTPUTS Each of the channel outputs has a rail-to-rail buffer. This enables all channels to have the capability to drive to within 50mV of the power rails, (see Electrical Characteristics for details). When driving large capacitive loads, a series resistor should be placed in series with the output. (Usually between 5 and 50). Each of the channels is updated on a continuous cycle, the time for the new data to appear at a specific output will depend on the exact timing relationship of the incoming data to this cycle. The best-case scenario is when the data has just been captured and then passed on to the output stage immediately; this can be as short as 48s. In the worst-case scenario this will be 480s for EL5226 and 576s for EL5236, when the data has just missed the cycle. When a large change in output voltage is required, the change will occur in 2V steps, thus the requisite number of timing cycles will be added to the overall update time. This means that a large change of 16V can take between 4.8ms and 5.3ms for EL5226 and between 6.9ms to 7.48ms for
EL5236 depending on the absolute timing relative to the update cycle. POWER DISSIPATION With the 30mA maximum continues output drive capability for each channel, it is possible to exceed the 125C absolute maximum junction temperature. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the part to remain in the safe operation. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA
where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation in the package
9
EL5226, EL5326
The maximum power dissipation actually produced by the IC is the total quiescent supply current times the total power supply voltage and plus the power in the IC due to the loads.
P DMAX = V S x I S + [ ( V S - V OUT i ) x I LOAD i ]
POWER SUPPLY BYPASSING AND PRINTED CIRCUIT BOARD LAYOUT Good printed circuit board layout is necessary for optimum performance. A low impedance and clean analog ground plane should be used for the EL5226 and EL5326. The traces from the two ground pins to the ground plane must be very short. The thermal pad of the EL5226 and EL5326 should be connected to the analog ground plane. Lead length should be as short as possible and all power supply pins must be well bypassed. A 0.1F ceramic capacitor must be place very close to the VS, VREFH, VREFL, and CAP pins. A 4.7F local bypass tantalum capacitor should be placed to the VS, VREFH, and VREFL pins. APPLICATION USING THE EL5226 AND EL5326 In the first application drawing, the schematic shows the interconnect of a pair of EL5226 and EL5326 chips connected to give 8 gamma corrected voltages above the VCOM voltage, and 8 gamma corrected voltages below the VCOM voltage.
when sourcing, and:
P DMAX = V S x I S + ( V OUT i x I LOAD i )
when sinking. Where: * i = 1 to total 12 * VS = Supply voltage * IS = Quiescent current * VOUTi = Output voltage of the i channel * ILOADi = Load current of the i channel By setting the two PDMAX equations equal to each other, we can solve for the RLOAD's to avoid the device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat.
10
EL5226, EL5326 Application Drawing
HIGH REFERENCE VOLTAGE +10V 0.1F +12V 0.1F MICROCONTROLLER +5V 0.1F OUTD AO I2C DATA IN I2C CLOCK LCD TIMING CONTROLLER HORIZONTAL RATE +5V SDA OUTE SCL OSC OSC_SEL CAP 0.1F OUTK REFL STD GND OUTL EL5226,EL5326 MIDDLE REFERENCE VOLTAGE OUTF ADDRESS = H74 VSD OUTC VS OUTB REFH OUTA
COLUMN (SOURCE) DRIVER
LCD PANEL
+5.5V
REFH OSC +5V +12V 0.1F OSC_SEL VS
OUTA
OUTB
+5V 0.1F I2C DATA IN I2C CLOCK
VSD
OUTC
AO SDA SCL CAP 0.1F
OUTD
OUTE
ADDRESS = H75
+1V
LOW REFERENCE VOLTAGE 0.1F
OUTF REFL OUTK
STD GND OUTL EL5226,EL5326
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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